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lt3845 1 3845fb typical application features applications description high voltage synchronous current mode step-down controller with adjustable operating frequency the lt ? 3845 is a high voltage, synchronous, current mode controller used for medium to high power, high ef? ciency supplies. it offers a wide 4v to 60v input range (7.5v minimum start-up voltage). an onboard regulator simpli? es the biasing requirements by providing ic power directly from v in . burst mode ? operation maintains high ef? ciency at light loads by reducing ic quiescent current to 120a. light load ef? ciency is also improved with the reverse inductor current inhibit function which supports discontinuous operation. additional features include adjustable ? xed operating frequency that can be synchronized to an external clock for noise sensitive applications, gate drivers capable of driving large n-channel mosfets, a precision undervoltage lockout, 10a shutdown current, short-circuit protection and a programmable soft-start. the lt3845 is available in a 16-lead thermally enhanced tssop package. high voltage operation: up to 60v synchronizable up to 600khz adjustable constant frequency: 100khz to 500khz output voltages up to 36v adaptive nonoverlap circuitry prevents switch shoot-through reverse inductor current inhibit for discontinuous operation improves ef? ciency with light loads programmable soft-start 120a no load quiescent current 10a shutdown supply current 1% regulation accuracy standard gate n-channel power mosfets current limit unaffected by duty cycle reverse overcurrent protection 16-lead thermally enhanced tssop package 12v and 42v automotive and heavy equipment 48v telecom power supplies avionics and industrial control systems distributed power converters , lt, ltc and ltm are registered trademarks of linear technology corporation. burst mode is a registered trademark of linear technology corporation. all other trademarks are the property of their respective owners. protected by u.s. patents, including 5481178, 6611131, 6304066, 6498466, 6580258. high voltage step-down regulator 48v to 12v at 75w v in shdn c ss burst_en v fb v c sync f set boost tg sw v cc bg pgnd sense + sense C sgnd bas521 1n4148 3845 ta01a 0.1 f 1500pf si7370dp si7370dp b160 15 h 0.01 lt3845 1 f 33 f 3 v out 12v 75w 1m 82.5k 16.2k v in 20v to 55v 2.2 f 100v 49.9k 10k 100pf 680pf 143k 47 f 63v load curent (a) 65 80 75 70 100 95 90 85 0 3 2 1 7 6 5 4 3845 ta01b efficiency(%) power loss (w) 0.1 10 1 v in = 48v loss ef? ciency and power loss vs load current
lt3845 2 3845fb package/order information electrical characteristics absolute maximum ratings (note 1) parameter conditions min typ max units v in operating voltage range (note 4) v in minimum start voltage v in uvlo threshold (falling) v in uvlo threshold hysteresis 4 3.6 3.8 670 60 7.5 4 v v v mv v in supply current v in burst mode current v in shutdown current v cc > 9v v burst_en = 0v, v fb = 1.35v v shdn = 0v 20 20 915 a a a boost operating voltage range boost operating voltage range (note 5) boost uvlo threshold (rising) boost uvlo threshold hysteresis v boost C v sw v boost C v sw v boost C v sw 5 400 75 20 v v v mv boost supply current (note 6) boost burst mode current boost shutdown current v burst_en = 0v v shdn = 0v 1.4 0.1 0.1 ma a a v cc operating voltage range (note 5) v cc output voltage v cc uvlo threshold (rising) v cc uvlo threshold hysteresis over full line and load range 8 6.25 500 20 8.3 v v v mv v cc supply current (note 6) v cc burst mode current v cc shutdown current v cc current limit v burst_en = 0v v shdn = 0v C40 3 100 20 C150 3.7 ma a a ma fe package 16-lead plastic tssop 1 2 3 4 5 6 7 8 top view 16 15 14 13 12 11 10 9 v in shdn c ss burst_en v fb v c sync f set boost tg sw v cc bg pgnd sense + sense C 17 t jmax = 125c, ja = 40c/w, jc = 10c/w exposed pad (pin 17) is sgnd, must be soldered to pcb order part number fe part marking* lt3845efe LT3845IFE 3845fe 3845fe order options tape and reel: add #tr lead free: add #pbf lead free tape and reel: add #trpbf lead free part marking: http://www.linear.com/leadfree/ consult ltc marketing for parts speci? ed with wider operating temperature ranges. *the temperature grade is identi? ed by a label on the shipping container. input supply voltage (v in ) ........................................65v boosted supply voltage (boost) .............................80v switch voltage (sw) (note 8) ....................... 65v to C2v differential boost voltage (boost to sw) .....................................................24v bias supply voltage (v cc ) .........................................24v sense + and sense C voltages ..................................40v differential sense voltage (sense + to sense C ) ................................... 1v to C1v burst_en voltage ...................................................24v sync, v c , v fb , c ss , and shdn voltages ....................5v shdn pin currents ..................................................1ma operating junction temperature range (note 2) lt3845e (note 3) ............................... C40c to 125c lt3845i ............................................. C40c to 125c storage temperature .............................. C65c to 150c lead temperature (soldering, 10 sec) .................. 300c the denotes the speci cations which apply over the full operating temperature range, otherwise speci cations are at t a = 25?. v in = 20v, v cc = boost = burst_en = 10v, shdn = 2v, r set = 49.9k , sense = sense + = 10v, sgnd = pgnd = sw = sync = 0v, unless otherwise noted.
lt3845 3 3845fb parameter conditions min typ max units error amp reference voltage measured at v fb pin 1.224 1.215 1.231 1.238 1.245 v v v fb pin input current v fb = 1.231v 25 na shdn enable threshold (rising) shdn threshold hysteresis 1.3 1.35 120 1.4 v mv sense pins common mode range current limit sense voltage reverse protect sense voltage reverse current inhibit offset v sense + C v sense C v sense + C v sense C , v burst_en = v cc v burst_en = 0v or v burst_en = v fb 0 90 100 C100 10 36 115 v mv mv mv input current (i sense + + i sense C )v sense(cm) = 0v v sense(cm) = 2v v sense(cm) > 4v 800 C20 C300 a a a operating frequency 290 270 300 310 330 khz khz minimum programmable frequency maximum programmable frequency 500 100 khz khz external sync frequency range 100 600 khz sync input resistance 40 k sync voltage threshold 1.4 2 v soft-start capacitor control current 2a error amp transconductance 270 340 410 s error amp dc voltage gain 62 db error amp sink/source current 30 a tg, bg drive on voltage (note 7) tg, bg drive off voltage c load = 3300pf c load = 3300pf 9.8 0.1 v v tg, bg drive rise/fall time 10% to 90% or 90% to 10%, c load = 3300pf 50 ns minimum tg off time 350 650 ns minimum tg on time 250 400 ns gate drive nonoverlap time tg fall to bg rise bg fall to tg rise 200 150 ns ns electrical characteristics the denotes the speci cations which apply over the full operating temperature range, otherwise speci cations are at t a = 25?. v in = 20v, v cc = boost = burst_en = 10v, shdn = 2v, r set = 49.9k , sense = sense + = 10v, sgnd = pgnd = sw = sync = 0v, unless otherwise noted. note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the lt3845 includes overtemperature protection that is intended to protect the device during momentary overload conditions. junction temperature will exceed 125c when overtemperature protection is active. continuous operation above the speci? ed maximum operating junction temperature may impair device reliability. note 3: the lt3845e is guaranteed to meet performance speci? cations from 0c to 125c junction temperature. speci? cations over the C 40c to 125c operating junction temperature range are assured by design, characterization and correlation with statistical process controls. the lt3845i is guaranteed over the full C40c to 125c operating junction temperature range. note 4: v in voltages below the start-up threshold (7.5v) are only supported when the v cc is externally driven above 6.5v. note 5: operating range is dictated by mosfet absolute maximum v gs . note 6: supply current speci? cation does not include switch drive currents. actual supply currents will be higher. note 7: dc measurement of gate drive output on voltage is typically 8.6v. internal dynamic bootstrap operation yields typical gate on voltages of 9.8v during standard switching operation. standard operation gate on voltage is not tested but guaranteed by design. note 8: the C2v absolute maximum on the sw pin is a transient condition. it is guaranteed by design and not subject to test.
lt3845 4 3845fb typical performance characteristics shutdown threshold (rising) vs temperature v cc vs temperature v cc vs i cc(load) i cc current limit vs temperature v cc uvlo threshold (rising) vs temperature i cc vs v cc (shdn = 0v) error amp transconductance vs temperature 3845 g01 shutdown threshold, rising (v) 1.38 1.37 1.36 1.35 1.34 1.33 1.32 temperature ( c) C50 25 75 C25 0 50 100 125 shutdown threshold (falling) vs temperature 3845 g02 temperature ( c) C50 shutdown threshold, falling (v) 1.26 1.25 1.24 1.23 1.22 1.21 1.20 25 75 C25 0 50 100 125 temperature ( c) C50 25 75 C25 0 50 100 125 3845 g03 8.2 8.1 8.0 7.9 7.8 7.7 7.6 7.5 v cc (v) i cc = 20ma i cc(load) (ma) 0 v cc (v) 40 10 20 30 8.05 8.00 7.95 7.90 7.85 51525 35 t a = 25 c v cc vs v in v in (v) v cc (v) 9 8 7 6 5 4 3 4 6 8 9 57 10 11 12 i cc = 20ma t a = 25 c C50 C25 100 0 50 125 25 75 temperature ( c) 225 200 175 150 125 100 75 50 i cc current limit (ma) 3845 g07 temperature ( c) C50 25 75 C25 0 50 100 125 v cc uvlo threshold, rising (v) 6.5 6.4 6.3 6.2 6.1 6.0 3845 g08 v cc (v) 0 i cc ( a) 15 20 25 16 10 5 0 246 810 12 14 18 20 t a = 25 c temperature ( c) C50 error amp transconductance ( s) 350 345 340 335 330 325 320 25 75 3845 g09 C25 0 50 100 125
lt3845 5 3845fb typical performance characteristics i (sense + + sense C ) vs v sense(cm) operating frequency vs temperature v sense(cm) (v) 0 0.5 1.5 2.5 3.5 4.5 i (sense + + sense C ) ( a) 800 600 400 200 0 C200 C400 1.0 2.0 3.0 4.0 5.0 t a = 25 c temperature ( c) C50 290 operating frequency (khz) 292 296 298 300 50 308 294 0 C25 75 100 25 125 302 304 306 temperature ( c) C50 25 75 3845 g12 C25 0 50 100 125 1.234 1.233 1.232 1.231 1.230 1.229 1.228 1.227 error amp reference (v) error amp reference vs temperature maximum current sense threshold vs temperature temperature ( c) C50 current sense threshold (mv) 102 104 106 25 75 100 98 C25 0 50 100 125 96 94 v in uvlo threshold (rising) vs temperature temperature ( c) C50 25 75 C25 0 50 100 125 3845 g14 4.54 4.52 4.50 4.48 4.46 4.44 4.42 4.40 v in uvlo threshold, rising (v) v in uvlo threshold (falling) vs temperature temperature ( c) C50 25 75 C25 0 50 100 125 3845 g15 v in uvlo threshold, falling (v) 3.86 3.84 3.82 3.80 3.78 3.76
lt3845 6 3845fb pin functions v in (pin 1): the v in pin is the main supply pin and should be decoupled to sgnd with a low esr capacitor (at least 0.1f) located close to the pin. shdn (pin 2): the shdn pin has a precision ic enable threshold of 1.35v (rising) with 120mv of hysteresis. it is used to implement an undervoltage lockout (uvlo) circuit. see application information section for implementing a uvlo function. when the shdn pin is pulled below a transistor v be (0.7v), a low current shutdown mode is entered, all internal circuitry is disabled and the v in supply current is reduced to approximately 9a. typical pin input bias current is <10na and the pin is internally clamped to 6v. if the function is not used, this pin may be tied to v in through a high value resistor. c ss (pin 3): the soft-start pin is used to program the supply soft-start function. use the following formula to calculate c ss for a given output voltage slew rate: c ss = 2a(t ss /1.231v) the pin should be left unconnected when not using the soft-start function. burst_en (pin 4): burst mode operation enable pin. this pin also controls reverse-current inhibit mode of operation. when the pin voltage is below 0.5v, burst mode operation and reverse-current inhibit functions are enabled. when the pin voltage is above 0.5v, burst mode operation is dis- abled, but reverse-current inhibit operation is maintained. in this mode of operation (burst_en = v fb ) there is a 1ma minimum load requirement. reverse-current inhibit is disabled when the pin voltage is above 2.5v. this pin is typically shorted to ground to enable burst mode operation and reverse-current inhibit, shorted to v fb to disable burst mode operation while enabling reverse-current inhibit, and connected to v cc pin to disable both functions. see applications information section. v fb (pin 5): the output voltage feedback pin, v fb , is externally connected to the supply output voltage via a resistive divider. the v fb pin is internally connected to the inverting input of the error ampli? er. in regulation, v fb is 1.231v. v c (pin 6): the v c pin is the output of the error ampli- ? er whose voltage corresponds to the maximum (peak) switch current per oscillator cycle. the error ampli? er is typically con? gured as an integrator by connecting an rc network from the v c pin to sgnd. this circuit creates the dominant pole for the converter regulation control loop. speci? c integrator characteristics can be con? gured to optimize transient response. when burst mode operation is enabled (see pin 4 description), an internal low imped- ance clamp on the v c pin is set at 100mv below the burst threshold, which limits the negative excursion of the pin voltage. therefore, this pin cannot be pulled low with a low impedance source. if the v c pin must be externally manipulated, do so through a 1k series resistance. sync (pin 7): the sync pin provides an external clock input for synchronization of the internal oscillator. r set is set such that the internal oscillator frequency is 10% to 25% below the external clock frequency. if unused the sync pin is connected to sgnd. for more information see oscillator sync in the application information section of this datasheet. f set (pin 8): the f set pin programs the oscillator frequency with an external resistor, r set . the resistor is required even when supplying external sync clock signal. see the applications information section for resistor value selec- tion details. sense C (pin 9): the sense C pin is the negative input for the current sense ampli? er and is connected to the v out side of the sense resistor for step-down applications. the sensed inductor current limit is set to 100mv across the sense inputs. sense + (pin 10): the sense + pin is the positive input for the current sense ampli? er and is connected to the induc- tor side of the sense resistor for step-down applications. the sensed inductor current limit is set to 100mv across the sense inputs. pgnd (pin 11): the pgnd pin is the high-current ground reference for internal low side switch driver and the v cc regulator circuit. connect the pin directly to the negative terminal of the v cc decoupling capacitor. see the applica- tion information section for helpful hints on pcb layout of grounds.
lt3845 7 3845fb bg (pin 12): the bg pin is the gate drive for the bottom n-channel mosfet. since very fast high currents are driven from this pin, connect it to the gate of the power mosfet with a short and wide, typically 0.02" width, pcb trace to minimize inductance. v cc (pin 13): the v cc pin is the internal bias supply decoupling node. use a low esr, 1f or greater ceramic capacitor to decouple this node to pgnd. most internal ic functions are powered from this bias supply. an external diode connected from v cc to the boost pin charges the bootstrapped capacitor during the off-time of the main power switch. back driving the v cc pin from an external dc voltage source, such as the v out output of the regula- tor supply, increases overall ef? ciency and reduces power dissipation in the ic. in shutdown mode this pin sinks 20a until the pin voltage is discharged to 0v. sw (pin 14): reference for v boost supply and high cur- rent return for bootstrapped switch. tg (pin 15): the tg pin is the bootstrapped gate drive for the top n-channel mosfet. since very fast high currents are driven from this pin, connect it to the gate of the power mosfet with a short and wide, typically 0.02 width, pcb trace to minimize inductance. pin functions boost (pin 16): the boost pin is the supply for the bootstrapped gate drive and is externally connected to a low esr ceramic boost capacitor referenced to sw pin. the recommended value of the boost capacitor,c boost , is at least 50 times greater than the total gate capacitance of the topside mosfet. in most applications 0.1f is adequate. the maximum voltage that this pin sees is v in + v cc , ground referred. sgnd (pin 17): the sgnd pin is the low noise ground reference. it should be connected to the Cv out side of the output capacitors. careful layout of the pcb is necessary to keep high currents away from this sgnd connection. see the application information section for helpful hints on pcb layout of grounds. exposed pad (sgnd) (pin 17): the exposed leadframe is internally connected to the sgnd pin. solder the exposed pad to the pcb ground for electrical contact and optimal thermal performance.
lt3845 8 3845fb block diagram C + C + C + C + C + v in uvlo (<4v) bst uvlo 8v reg feedback reference C + 1.231v 3.8v reg internal supply rail 1 16 15 14 11 2 4 6 3 5 v in v cc uvlo (<6v) shdn v ref drive control nol switch logic drive control burst_en r b v c c ss sense C v fb C + v ref + 100mv fault conditions: v in uvlo v cc uvlo v shdn uvlo 2 a 1v 0.5v 100mv error amp burst mode operation 9 soft-start burst disable c ss clamped to v ref + v be r s q oscillator slope comp generator boost c boost m1 tg driver driver sw v cc 12 bg pgnd 7 sync f set r set sense + 3845 fd boosted switch driver current sense comparator g m C+ C + r s q C + 110mv reverse current inhibit 10mv C + 17 sgnd 8 m2 c out v out r sense d2 (optional) l1 d1 c vcc 10 c in v in r c c c1 r2 r1 r a c ss c c2 13
lt3845 9 3845fb applications information overview the lt3845 is a high input voltage range step-down synchronous dc/dc converter controller ic that uses a programmable constant frequency, current mode archi- tecture with external n-channel mosfet switches. the lt3845 has provisions for high ef? ciency, low load operation for battery-powered applications. burst mode operation reduces total average input quiescent currents to 120a during no load conditions. a low current shutdown mode can also be activated, reducing quiescent current to 10a. burst mode operation can be disabled if desired. a reverse-current inhibit feature allows increased ef? cien- cies during light loads through nonsynchronous operation. this feature disables the synchronous switch if inductor current approaches zero. if full time synchronous opera- tion is desired, this feature can be disabled. much of the ics internal circuitry is biased from an internal linear regulator. the output of this regulator is the v cc pin, allowing bypassing of the internal regulator. the associated internal circuitry can be powered from the output of the converter, increasing overall converter ef? ciency. using externally derived power also eliminates the ics power dissipation associated with the internal v in to v cc regulator. theory of operation (see block diagram) the lt3845 senses converter output voltage via the v fb pin. the difference between the voltage on this pin and an internal 1.231v reference is ampli? ed to generate an error voltage on the v c pin which is used as a threshold for the current sense comparator. during normal operation, the lt3845 internal oscillator runs at the programmed frequency. at the beginning of each oscillator cycle, the switch drive is enabled. the switch drive stays enabled until the sensed switch current exceeds the v c derived threshold for the current sense comparator and, in turn, disables the switch driver. if the current comparator threshold is not obtained for the entire oscillator cycle, the switch driver is disabled at the end of the cycle for 350ns, typical. this minimum off-time mode of operation assures regeneration of the boost bootstrapped supply. power requirements the lt3845 is biased using an internal linear regulator to generate operational voltages from the v in pin. virtually all of the circuitry in the lt3845 is biased via this internal linear regulator output (v cc ). this pin is decoupled with a low esr, 1f capacitor to pgnd. the v cc regulator generates an 8v output provided there is ample voltage on the v in pin. the v cc regulator has approximately 1v of dropout, and will follow the v in pin with voltages below the dropout threshold. the lt3845 has a start-up requirement of v in > 7.5v. this assures that the onboard regulator has ample headroom to bring the v cc pin above its uvlo threshold. the v cc regulator can only source current, so forcing the v cc pin above its 8v regulated voltage allows use of externally derived power for the ic, minimizing power dissipation in the ic. using the onboard regulator for start-up, then deriving power for v cc from the converter output maxi- mizes conversion ef? ciencies and is common practice. if v cc is maintained above 6.5v using an external source, the lt3845 can continue to operate with v in as low as 4v. the lt3845 operates with 3ma quiescent current from the v cc supply. this current is a fraction of the actual v cc quiescent currents during normal operation. additional current is produced from the mosfet switching currents for both the boosted and synchronous switches and are typically derived from the v cc supply. because the lt3845 uses a linear regulator to generate v cc , power dissipation can become a concern with high v in voltages. gate drive currents are typically in the range of 5ma to 15ma per mosfet, so gate drive currents can create substantial power dissipation. it is advisable to derive v cc and v boost power from an external source whenever possible. the onboard v cc regulator will provide gate drive power for start-up under all conditions with total mosfet gate charge loads up to 180nc. the regulator can operate the lt3845 continuously, provided the power dissipation of the regulator does not exceed 250mw. the power dissipaton of the regulator is calculated as follows: p d(reg) = (v in C 8v) ? (f sw ? q g(total) + 3ma)
lt3845 10 3845fb where q g(total) is the total mosfet gate charge of the tg and bg. in applications where these conditions are exceeded, v cc must be derived from an external source after start-up. maximum continuous regulator power dissipation may be exceeded for short duration v in transients. in lt3845 converter applications with output voltages in the 9v to 20v range, back-feeding v cc and v boost from the converter output is trivial, accomplished by connect- ing diodes from the output to these supply pins. deriving these supplies from output voltages greater than 20v will require additional regulation to reduce the feedback voltage. outputs lower than 9v will require step-up techniques to increase the feedback voltage to something greater than the 8v v cc regulated output. low power boost switchers are sometimes used to provide the step-up function, but a simple charge-pump can perform this function in many instances. burst mode the lt3845 employs low current burst mode functional- ity to maximize ef? ciency during no load and low load conditions. burst mode operation is enabled by shorting the burst_en pin to sgnd. burst mode operation can be disabled by shorting burst_en to either v fb or v cc . when the required switch current, sensed via the v c pin voltage, is below 15% of maximum, the burst mode operation is employed and that level of sense current is latched onto the ic control path. if the output load requires less than this latched current level, the converter will overdrive the output slightly during each switch cycle. this overdrive condition is sensed internally and forces the voltage on the v c pin to continue to drop. when the voltage on v c drops 150mv below the 15% load level, switching is disabled and the lt3845 shuts down most of its internal circuitry, reducing total quiescent current to 120a. when the converter output begins to fall, the v c pin voltage begins to climb. when the voltage on the v c pin climbs back to the 15% load level, the ic returns to normal operation and switching resumes. an internal clamp on the v c pin is set at 100mv below the switch disable threshold, which limits the negative excursion of the pin voltage, minimizing the converter output ripple during burst mode operation. during burst mode operation, v in pin current is 20a and v cc current is reduced to 100a. if no external drive is provided for v cc , all v cc bias currents originate from the applications information v out 1 f b0520 b0520 1 f si1555dl lt3845 charge pump doubler charge pump tripler v cc bg v out 1 f b0520 b0520 1 f 1 f si1555dl si1555dl lt3845 v cc bg b0520 3845 ai01 tg v out 3845 ai04 v cc sw bg n ? ? lt3845 inductor auxiliary winding
lt3845 11 3845fb applications information v in pin, giving a total v in current of 120a. burst current can be reduced further when v cc is driven using an output derived source, as the v cc component of v in current is then reduced by the converter buck ratio. reverse-current inhibit the lt3845 contains a reverse-current inhibit feature to maximize ef? ciency during light load conditions. this mode of operation allows discontinuous operation and pulse-skipping mode at light loads. refer to figure 1. this feature is enabled with burst mode operation, and can also be enabled while burst mode operation is disabled by shorting the burst_en pin to v fb . when reverse-current inhibit is enabled, the lt3845 sense ampli? er detects inductor currents approaching zero and disables the synchronous switch for the remainder of the switch cycle. if the inductor current is allowed to go negative before the synchronous switch is disabled, the switch node could inductively kick positive with a high dv/dt. the lt3845 prevents this by incorporating a 10mv positive offset at the sense inputs. with the reverse-current inhibit feature enabled, an lt3845 converter will operate much like a nonsynchronous converter during light loads. reverse-current inhibit reduces resistive losses associated with inductor ripple currents, which improves operating ef? ciencies during light-load conditions. an lt3845 dc/dc converter that is operating in reverse- current inhibit mode has a minimum load requirement of 1ma (burst_en = v fb ). since most applications use output-generated power for the lt3845, this require- ment is met by the bias currents of the ic, however, for applications that do not derive power from the output, this requirement is easily accomplished by using a 1.2k resistor connected from v fb to ground as one of the converter output voltage programming resistors (r1). there are no minimum load restrictions when in burst mode operation (burst_en < 0.5v) or continuous conduction mode (burst_en > 2.5v). soft-start the soft-start function controls the slew rate of the power supply output voltage during start-up. a controlled output voltage ramp minimizes output voltage overshoot, reduces inrush current from the v in supply, and facilitates supply sequencing. a capacitor, c ss , connected from the c ss pin to sgnd, programs the slew rate. the capacitor is charged from an internal 2a current source producing a ramped voltage. the capacitor voltage overrides the internal refer- ence to the error ampli? er. if the v fb pin voltage exceeds the c ss pin voltage then the current threshold set by the dc control voltage, v c , is decreased and the inductor cur- rent is lowered. this in turn decreases the output voltage slew rate allowing the c ss pin voltage ramp to catch up to the v fb pin voltage. an internal 100mv offset is added to the v fb pin voltage relative to the c ss pin voltage so that figure 1. inductor current vs mode pulse skip mode i l i l forced continuous decreasing load current 3845 f01
lt3845 12 3845fb at start-up the soft-start circuit will discharge the v c pin voltage below the dc control voltage equivalent to zero inductor current. this will reduce the input supply inrush current. the soft-start circuit is disabled once the c ss pin voltage has been charged to 200mv above the internal reference of 1.231v. during a v in uvlo, v cc uvlo or shdn uvlo event, the c ss pin voltage is discharged with a 50a current source. in normal operation the c ss pin voltage is clamped to a diode above the v fb pin voltage. therefore, the value of the c ss capacitor is relevant to how long of a fault event will retrigger a soft-start. if any of the above uvlo conditions occur, the c ss pin voltage will be discharged with a 50a current source. there is a diode worth of voltage headroom to ride through the fault before the c ss pin voltage enters its active region and the soft-start function is enabled. also, since the c ss pin voltage is clamped to a diode above the v fb pin voltage, during a short circuit the c ss pin volt- age is pulled low because the v fb pin voltage is low. once the short has been removed the v fb pin voltage starts to recover. the soft-start circuit takes control of the output voltage slew rate once the v fb pin voltage has exceeded the slowly ramping c ss pin voltage, reducing the output voltage overshoot during a short circuit recovery. adaptive nonoverlap (nol) output stage the fet driver output stages implement adaptive nonover- lap control. this feature maintains a constant dead time, preventing shoot-through switch currents, independent of the type, size or operating conditions of the external switch elements. each of the two switch drivers contains a nol control circuit, which monitors the output gate drive signal of the other switch driver. the nol control circuits interrupt the turn on command to their associated switch driver until the other switch gate is fully discharged. antislope compensation most current mode switching controllers use slope com- pensation to prevent current mode instability. the lt3845 is no exception. a slope-compensation circuit imposes an arti? cial ramp on the sensed current to increase the rising slope as duty cycle increases. unfortunately, this additional applications information ramp corrupts the sensed current value, reducing the achievable current limit value by the same amount as the added ramp represents. as such, current limit is typically reduced as duty cycles increase. the lt3845 contains circuitry to eliminate the current limit reduction typically associated with slope compensation. as the slope-com- pensation ramp is added to the sensed current, a similar ramp is added to the current limit threshold reference. the end result is that current limit is not compromised, so an lt3845 converter can provide full power regardless of required duty cycle. shutdown the lt3845 shdn pin uses a bandgap generated reference threshold of 1.35v. this precision threshold allows use of the shdn pin for both logic-level controlled applications and analog monitoring applications such as power supply sequencing. the lt3845 operational status is primarily controlled by a uvlo circuit on the v cc regulator pin. when the ic is enabled via the shdn pin, only the v cc regulator is enabled. switching remains disabled until the uvlo threshold is achieved at the v cc pin, when the remainder of the ic is enabled and switching commences. because an lt3845 controlled converter is a power transfer device, a voltage that is lower than expected on the input supply could require currents that exceed the sourcing capabilities of that supply, causing the system to lock up in an undervoltage state. input supply start-up protection can be achieved by enabling the shdn pin using a resistive divider from the v in supply to ground. setting the divider output to 1.35v when that supply is at an adequate voltage prevents an lt3845 converter from drawing large currents until the input supply is able to provide the required power. 120mv of input hysteresis on the shdn pin allows for almost 10% of input supply droop before disabling the converter. r sense selection the current sense resistor, r sense , monitors the inductor current of the supply (see typical application on front page). its value is chosen based on the maximum required output load current. the lt3845 current sense ampli? er
lt3845 13 3845fb has a maximum voltage threshold of, typically, 100mv. therefore, the peak inductor current is 100mv/r sense . the maximum output load current, i out(max) , is the peak inductor current minus half the peak-to-peak ripple cur- rent, i l . allowing adequate margin for ripple current and exter- nal component tolerances, r sense can be calculated as follows: r mv i sense out max = 70 () typical values for r sense are in the range of 0.005 to 0.05 . operating frequency the choice of operating frequency is a trade off between ef? ciency and component size. low frequency operation improves ef? ciency by reducing mosfet switching losses and gate charge losses. however, lower frequency opera- tion requires more inductance for a given amount of ripple current, resulting in a larger inductor size and higher cost. if the ripple current is allowed to increase, larger output capacitors may be required to maintain the same output ripple. for converters with high step-down v in to v out ratios, another consideration is the minimum on-time of the lt3845 (see the minimum on-time considerations section). a ? nal consideration for operating frequency is that in noise-sensitive communications systems, it is often desirable to keep the switching noise out of a sensitive frequency band. the lt3845 uses a constant frequency applications information architecture that can be programmed over a 100khz to 500khz range with a single resistor from the f set pin to ground, as shown in figure 2. the nominal voltage on the f set pin is 1v and the current that ? ows from this pin is used to charge an internal oscillator capacitor. the value of r set for a given operating frequency can be chosen from figure 2 or from the following equation: r set(k ) = 8.4 ? 10 4 ? f sw (C1.31) table 1 lists typical resistor values for common operating frequencies. table 1. recommended 1% standard values r set f sw 191k 100khz 118k 150khz 80.6k 200khz 63.4k 250khz 49.9k 300khz 40.2k 350khz 33.2k 400khz 27.4k 450khz 23.2k 500khz inductor selection the critical parameters for selection of an inductor are minimum inductance value, volt-second product, satura- tion current and/or rms current. for a given i l , the minimum inductance value is calcu- lated as follows: lv vv fv i out in max out sw in max l ? C ?? () () f sw is the switch frequency. the typical range of values for i l is (0.2 ? i out(max) ) to (0.5 ? i out(max) ), where i out(max) is the maximum load current of the supply. using i l = 0.3 ? i out(max) yields a good design compromise between inductor performance versus inductor size and cost. a value of i l = 0.3 ? i out(max) produces a 15% of i out(max) ripple current around the dc output current of the supply. lower values of i l require larger and more costly magnetics. higher values of i l frequency (khz) 0 20 r set (k ) 40 80 100 120 400 200 60 200 100 500 300 600 140 160 180 figure 2. timing resistor (r set ) value
lt3845 14 3845fb applications information will increase the peak currents, requiring more ? ltering on the input and output of the supply. if i l is too high, the slope compensation circuit is ineffective and current mode instability may occur at duty cycles greater than 50%. to satisfy slope compensation requirements the minimum inductance is calculated as follows: lv dc dc r f min out max max sense sw > ? C ? ?. 21 833 the magnetics vendors specify either the saturation cur- rent, the rms current or both. when selecting an inductor based on inductor saturation current, use the peak current through the inductor, i out(max) + i l /2. the inductor saturation current speci? cation is the current at which the inductance, measured at zero current, decreases by a speci? ed amount, typically 30%. when selecting an inductor based on rms current rating, use the average current through the inductor, i out(max) . the rms current speci? cation is the rms current at which the part has a speci? c temperature rise, typically 40c, above 25c ambient. after calculating the minimum inductance value, the volt-second product, the saturation current and the rms current for your design, select an off-the-shelf inductor. contact the application group at linear technology for further support. for more detailed information on selecting an inductor, please see the inductor selection section of linear technology application note 44. mosfet selection the selection criteria of the external n-channel standard level power mosfets include on resistance (r ds(on) ), reverse transfer capacitance (c rss ), maximum drain source voltage (v dss ), total gate charge (q g ) and maximum continuous drain current. for maximum ef? ciency, minimize r ds(on) and c rss . low r ds(on) minimizes conduction losses while low c rss minimizes transition losses. the problem is that r ds(on) is inversely related to c rss . in selecting the top mosfet balancing the transition losses with the conduction losses is a good idea while the bottom mosfet is dominated by the conduction loss, which is worse during a short-circit condition or at a very low duty cycle. calculate the maximum conduction losses of the mosfets: pi v v r p cond top out max out in ds on cond () ( ) () ( ?? = 2 b bot out max in out in ds on i vv v r )() () ? C ? = 2 note that r ds(on) has a large positive temperature depen- dence. the mosfet manufacturers data sheet contains a curve, r ds(on) vs temperature. in the main mosfet, transition losses are proportional to v in 2 and can be considerably large in high voltage ap- plications (v in > 20v). calculate the maximum transition losses: p tran(top) = k ? v in 2 ? i out(max) ? c rss ? f sw where k is a constant inversely related to the gate driver current, approximated by k = 2 for lt3845 applications. the total maximum power dissipations of the mosfet are: p top(total) = p cond(main) + p tran(main) p bot(total) = p cond(sync) to achieve high supply ef? ciency, keep the total power dis- sipation in each switch to less than 3% of the total output power. also, complete a thermal analysis to ensure that the mosfet junction temperature is not exceeded. t j = t a + p (total) ? ja where ja is the package thermal resistance and t a is the ambient temperature. keep the calculated t j below the max- imum speci? ed junction temperature, typically 150c. note that when v in is high and f sw is high, the transition losses may dominate. a mosfet with higher r ds(on) and lower c rss may provide higher ef? ciency. mosfets with higher voltage v dss speci? cation usually have higher r ds(on) and lower c rss .
lt3845 15 3845fb applications information choose the mosfet v dss speci? cation to exceed the maximum voltage across the drain to the source of the mosfet, which is v in(max) plus any additional ringing on the switch node. ringing on the switch node can be greatly reduced with good pcb layout and, if necessary, an rc snubber. in some applications, parasitic fet capacitances couple the negative going switch node transient onto the bottom gate drive pin of the lt3845, causing a negative voltage in excess of the absolute maximum rating to be imposed on that pin. connection of a catch schottky diode from this pin to ground will eliminate this effect. a 1a current rating is typically suf? cient of the diode. the internal v cc regulator is capable of sourcing up to 40ma limiting the maximum total mosfet gate charge, q g , to 35ma/f sw . the q g vs v gs speci? cation is typically provided in the mosfet data sheet. use q g at v gs of 8v. if v cc is back driven from an external supply, the mosfet drive current is not sourced from the internal regulator of the lt3845 and the q g of the mosfet is not limited by the ic. however, note that the mosfet drive current is supplied by the internal regulator when the external supply back driving v cc is not available such as during start-up or short circuit. the manufacturers maximum continuous drain current speci? cation should exceed the peak switch current, i out(max) + i l /2. during the supply start-up, the gate drive levels are set by the v cc voltage regulator, which is approximately 8v. once the supply is up and running, the v cc can be back driven by an auxiliary supply such as v out . it is important not to exceed the manufacturers maximum v gs speci? cation. a standard level threshold mosfet typically has a v gs maximum of 20v. input capacitor selection a local input bypass capacitor is required for buck convert- ers because the input current is pulsed with fast rise and fall times. the input capacitor selection criteria are based on the bulk capacitance and rms current capability. the bulk capacitance will determine the supply input ripple voltage. the rms current capability is used to prevent overheating the capacitor. the bulk capacitance is calculated based on maximum input ripple, v in : c iv vf v in bulk out max out in sw in min () () () ? ?? = v in is typically chosen at a level acceptable to the user. 100mv to 200mv is a good starting point. aluminum elec- trolytic capacitors are a good choice for high voltage, bulk capacitance due to their high capacitance per unit area. the capacitors rms current is: ii vvv v cin rms out out in out in () (C ) () = 2 if applicable, calculate it at the worst case condition, v in = 2v out . the rms current rating of the capacitor is speci? ed by the manufacturer and should exceed the calculated i cin(rms) . due to their low esr (equivalent series resistance), ceramic capacitors are a good choice for high voltage, high rms current handling. note that the ripple current ratings from aluminum electrolytic capacitor manufacturers are based on 2000 hours of life. this makes it advisable to further derate the capacitor or to choose a capacitor rated at a higher temperature than required. the combination of aluminum electrolytic capacitors and ceramic capacitors is an economical approach to meet- ing the input capacitor requirements. the capacitor volt- age rating must be rated greater than v in(max) . multiple capacitors may also be paralleled to meet size or height requirements in the design. locate the capacitor very close to the mosfet switch and use short, wide pcb traces to minimize parasitic inductance. output capacitor selection the output capacitance, c out , selection is based on the designs output voltage ripple, v out and transient load requirements. v out is a function of i l and the c out esr. it is calculated by: = + ? ? ? ? ? ? v i esr fc out l sw out ? (? ? ) 1 8
lt3845 16 3845fb the maximum esr required to meet a v out design requirement can be calculated by: esr max vlf v v v out sw out out in max () ()()() ?C () = 1 ?? ? ? ? ? ? worst-case v out occurs at highest input voltage. use paralleled multiple capacitors to meet the esr require- ments. increasing the inductance is an option to lower the esr requirements. for extremely low v out , an additional lc ? lter stage can be added to the output of the supply. application note 44 has some good tips on sizing an ad- ditional output ? lter. output voltage programming a resistive divider sets the dc output voltage according to the following formula: rr v v out 21 1 231 1 = ? ? ? ? ? ? . C the external resistor divider is connected to the output of the converter as shown in figure 3. tolerance of the feedback resistors will add additional error to the output voltage. example: v out = 12v; r1 = 10k rk v v kuse k 210 12 1 231 1 8748 866 1 = ? ? ? ? ? ? ? =? . ..% % the v fb pin input bias current is typically 25na, so use of extremely high value feedback resistors could cause a converter output that is slightly higher than expected. bias current error at the output can be estimated as: v out(bias) = 25na ? r2 supply uvlo and shutdown the shdn pin has a precision voltage threshold with hysteresis which can be used as an undervoltage lockout threshold (uvlo) for the power supply. undervoltage lockout keeps the lt3845 in shutdown until the supply input voltage is above a certain voltage programmed by the user. the hysteresis voltage prevents noise from falsely tripping uvlo. resistors are chosen by ? rst selecting r b . then rr v v ab supply on = ? ? ? ? ? ? ? . C () 135 1 v supply(on) is the input voltage at which the undervoltage lockout is disabled and the supply turns on. example: select r b = 49.9k , v supply(on) = 14.5v (based on a 15v minimum input voltage) rk v v a = ? ? ? ? ? ? = 49 9 14 5 135 1 .? . . C 486.1k (499k ? resistor is selected) applications information l1 v fb pin r2 r1 v out c out 3845 f03 shdn pin r a r b v supply 3845 f04 figure 3. output voltage feedback divider figure 4. undervoltage feedback divider
lt3845 17 3845fb if low supply current in standby mode is required, select a higher value of r b . the supply turn off voltage is 9% below turn on. in the example the v supply(off) would be 13.2v. if additional hysteresis is desired for the enable function, an external positive feedback resistor can be used from the lt3845 regulator output. the shutdown function can be disabled by connecting the shdn pin to the v in through a large value pull-up resistor. this pin contains a low impedance clamp at 6v, so the shdn pin will sink current from the pull-up resistor(r pu ): i vv r shdn in pu = C6 because this arrangement will clamp the shdn pin to the 6v, it will violate the 5v absolute maximum voltage rating of the pin. this is permitted, however, as long as the absolute maximum input current rating of 1ma is not exceeded. input shdn pin currents of <100a are recommended: a 1m or greater pull-up resistor is typically used for this con? guration. soft-start the desired soft-start time (t ss ) is programmed via the c ss capacitor as follows: c a t v ss ss = 2 1 231 ? . the amount of time in which the power supply can withstand a v in , v cc or v shdn uvlo fault condition (t fault ) before the c ss pin voltage enters its active region is approximated by the following formula: t cv a fault ss = ?. 065 50 oscillator sync the oscillator can be synchronized to an external clock. set the r set resistor at least 10% below the desired sync frequency. it is recommended that the sync pin be driven with a square wave that has amplitude greater than 2v, pulse width greater than 1 s and rise time less than 500ns. the rising edge of the sync wave form triggers the discharge of the internal oscillator capacitor. minimum on-time considerations (buck mode) minimum on-time t on(min) is the smallest amount of time that the lt3845 is capable of turning the top mosfet on and off again. it is determined by internal timing delays and the amount of gate charge required turning on the top mosfet. low duty cycle applications may approach this minimum on-time limit and care should be taken to ensure that: t v vf t on out in sw on min => ? () where t on(min) is 400ns worst case. if the duty cycle falls below what can be accommodated by the minimum on-time, the lt3845 will begin to skip cycles. the output will be regulated, but the ripple current and ripple voltage will increase. if lower frequency opera- tion is acceptable, the on-time can be increased above t on(min) for the same step-down ratio. layout considerations the lt3845 is typically used in dc/dc converter designs that involve substantial switching transients. the switch drivers on the ic are designed to drive large capacitances and, as such, generate signi? cant transient currents themselves. careful consideration must be made regard- ing supply bypass capacitor locations to avoid corrupting the ground reference used by ic. typically, high current paths and transients from the input supply and any local drive supplies must be kept isolated from sgnd, to which sensitive circuits such as the error amp reference and the current sense circuits are referred. effective grounding can be achieved by considering switch current in the ground plane, and the return current paths of each respective bypass capacitor. the v in bypass return, v cc bypass return, and the source of the synchronous applications information
lt3845 18 3845fb fet carry pgnd currents. sgnd originates at the negative terminal of the v out bypass capacitor, and is the small signal reference for the lt3845. dont be tempted to run small traces to separate ground paths. a good ground plane is important as always, but pgnd referred bypass elements must be oriented such that transient currents in these return paths do not corrupt the sgnd reference. during the dead-time between switch conduction, the body diode of the synchronous fet conducts inductor current. commutating this diode requires a signi? cant charge contribution from the main switch. at the instant the body diode commutates, a current discontinuity is created and parasitic inductance causes the switch node to ? y up in response to this discontinuity. high currents and excessive parasitic inductance can generate ex- tremely fast dv/dt rise times. this phenomenon can cause avalanche breakdown in the synchronous fet body di- ode, signi? cant inductive overshoot on the switch node, and shoot-through currents via parasitic turn-on of the synchronous fet. layout practices and component ori- entations that minimize parasitic inductance on this node is critical for reducing these effects. ringing waveforms in a converter circuit can lead to device failure, excessive emi, or instability. in many cases, you can damp a ringing waveform with a series rc network across the offending device. in lt3845 applications, any ringing will typically occur on the switch node, which can usually be reduced by placing a snubber across the synchronous fet. use of a snubber network, however, should be considered a last resort. effective layout practices typically reduce ringing and overshoot, and will eliminate the need for such solutions. effective grounding techniques are critical for successful dc/dc converter layouts. orient power path components such that current paths in the ground plane do not cross through signal ground areas. signal ground refers to the exposed pad on the backside of the lt3845 ic. sgnd is referenced to the (C) terminal of the v out decoupling capacitor and is used as the converter voltage feedback reference. power ground currents are controlled on the lt3845 via the pgnd pin, and this ground references the high current synchronous switch drive components, as well as the local v cc supply. it is important to keep pgnd and sgnd voltages consistent with each other, so separating these grounds with thin traces is not recom- mended. when the synchronous fet is turned on, gate drive surge currents return to the lt3845 pgnd pin from the fet source. the boost supply refresh surge currents also return through this same path. the synchronous fet must be oriented such that these pgnd return currents do not corrupt the sgnd reference. problems caused by the pgnd return path are generally recognized during heavy load conditions, and are typically evidenced as multiple switch pulses occurring during a single switch cycle. this behavior indicates that sgnd is being corrupted and grounding should be improved. sgnd corruption can often be eliminated, however, by adding a small capacitor (100pf to 200pf) across the synchronous switch fet from drain to source. the high di/dt loop formed by the switch mosfets and the input capacitor (c in ) should have short wide traces to minimize high frequency noise and voltage stress from inductive ringing. surface mount components are preferred to reduce parasitic inductances from component leads. connect the drain of the main switch mosfet directly to the (+) plate of c in , and connect the source of the syn- chronous switch mosfet directly to the (C) terminal of c in . this capacitor provides the ac current to the switch mosfets. switch path currents can be controlled by orienting switch fets, the switched inductor, and input and output decoupling capacitors in close proximity to each other. locate the v cc and boost decoupling capacitors in close proximity to the ic. these capacitors carry the mosfet drivers high peak currents. locate the small-signal components away from high frequency switching nodes (boost, sw, tg, v cc and bg). small-signal nodes are oriented on the left side of the lt3845, while high current switching nodes are oriented on the right side of the ic to simplify layout. this also helps prevent corruption of the sgnd reference. connect the v fb pin directly to the feedback resistors independent of any other nodes, such as the sense C pin. the feedback resistors should be connected between the (+) and (C) terminals of the output capacitor (c out ). applications information
lt3845 19 3845fb locate the feedback resistors in close proximity to the lt3845 to minimize the length of the high impedance v fb node. the sense C and sense + traces should be routed together and kept as short as possible. applications information the lt3845 packaging has been designed to ef? ciently remove heat from the ic via the exposed pad on the backside of the package. the exposed pad is soldered to a copper footprint on the pcb. this footprint should be made as large as possible to reduce the thermal resistance of the ic case to ambient air. orientation of components isolates power path and pgnd currents, preventing corruption of sgnd reference boost v cc sw pgnd sgnd lt3845 sgnd referred components + + bg tg v out 3845 ai03 v in i sense sw
lt3845 20 3845fb typical applications 9v-16v to 3.3v at 10a dc/dc converter capable of withstanding 60v transients, all ceramic capacitors and soft-start enabled v in shdn c ss burst_en v fb v c sync f set 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 boost tg sw v cc bg pgnd sense + sense C sgnd d2a bav99 c5 1 f 16v c3 8200pf m1 si7370dp m2 si7370dp d1 l1 3.3 h r sense 0.006 lt3845 c4 2.2 f 16v 3845 ta02 17 c2 6800pf c out 100 f 6.3v 5 v out 3.3v 10a r3 1.1m v in 9v to 16v 60v transients c in2 0.1 f 100v r6 49.9k v in r5 100k sync r7 4.99k d3 12v r4 25k r1 10k r2 16.9k c in 2.2 f 100v 4 c in : tdk c4532x7r2a225k c out : murata grm32er60j107me20 d1: diodes inc. b3100 l1: wurth 7443551370 d2b bav99 q1 60v load current (a) 0.1 65 battery voltage (v) power loss (w) 70 75 80 85 95 110 3845 ta02b 90 0 1 2 3 4 6 5 v in = 9v v in = 14v v in = 16v power loss v in = 14v ef? ciency and power loss
lt3845 21 3845fb typical applications 9v-16v to 5v at 10a dc/dc converter, 500khz frequency operation, capable of withstanding 36v transients, all ceramic capacitors, soft-start and burst mode enabled v in shdn c ss burst_en v fb v c sync f set 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 boost tg sw v cc bg pgnd sense + sense C sgnd d2 bas19 c5 1 f 16v c3 8200pf m1 si7884dp m2 si7884dp si1555dl d1 l1 2.7 h r sense 0.005 lt3845 c4 2.2 f 16v c6 1 f d3b bav99 d3a bav99 3845 ta03 17 c2 5600pf c1 100pf c out 100 f 6.3v 4 v out 5v 10a r3 1.1m v in 9v to 16v 36v transients c in2 0.1 f 50v r6 23.2k r4 10k r1 49.9k r2 154k c in 6.8 f 50v 4 c in : tdk c4532x7r1h685k c out : murata grm32er60j107me20 d1: diodes inc. b170 l1: wurth 744318270lf ef? ciency and power loss load current (a) 0.1 70 efficiency (%) power loss (w) 75 80 85 90 100 110 3845 ta03b 95 0 1 2 3 4 6 5 v in = 9v v in = 14v v in = 16v power loss v in = 14v
lt3845 22 3845fb typical applications 9v-24v to 3.3v, 2-phase at 10a per phase, dc/dc converter with spread spectrum operation v in shdn c ss burst_en v fb v c sync f set 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 boost tg sw v cc bg pgnd sense + sense C sgnd c5 1 f 16v d2 bas19 c3 8200pf c11 47pf m1 si7850dp m2 si7850dp d1 b160 l1 4.7 h r sense 0.005 lt3845 c4 2.2 f 16v 17 r3 1.21m r4 1.21m v in 24v r6 130k sync c in 6.8 f 50v 2 c in : tdk c4532x7r1h685k c out : murata grm32er60j107me20 d1, d3: diodes, inc. b160 l1, l2: vishay ihlp-5050fd-01 v in shdn c ss burst_en v fb v c sync f set 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 boost tg sw v cc bg pgnd sense + sense C sgnd c10 1 f 16v c8 8200pf m3 si7850dp m4 si7850dp d3 b160 l2 4.7 h r sense2 0.005 lt3845 c9 2.2 f 16v 3845 ta05 17 r10 130k r9 4.99k c7 5600pf c6 47pf c in3 0.1 f 100v sync1 sync2 sync r1 10k r11 500k r12 25k d5 5.7v c11 0.1 f q1 r2 16.8k ltc6908-1 v + gnd set3 6 5 4 1 2 3 out1 out2 mod c out 100 f 6.3v 6 v out 3.3v 20a d4 bas19
lt3845 23 3845fb information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. package description fe package 16-lead plastic tssop (4.4mm) (reference ltc dwg # 05-08-1663) exposed pad variation bc fe16 (bc) tssop 0204 0.09 C 0.20 (.0035 C .0079) 0 C 8 0.25 ref 0.50 C 0.75 (.020 C .030) 4.30 C 4.50* (.169 C .177) 134 5 6 7 8 10 9 4.90 C 5.10* (.193 C .201) 16 1514 13 12 11 1.10 (.0433) max 0.05 C 0.15 (.002 C .006) 0.65 (.0256) bsc 2.94 (.116) 0.195 C 0.30 (.0077 C .0118) typ 2 recommended solder pad layout 0.45 0.05 0.65 bsc 4.50 0.10 6.60 0.10 1.05 0.10 2.94 (.116) 3.58 (.141) 3.58 (.141) millimeters (inches) *dimensions do not include mold flash. mold flash shall not exceed 0.150mm (.006") per side note: 1. controlling dimension: millimeters 2. dimensions are in 3. drawing not to scale see note 4 4. recommended minimum pcb metal size for exposed pad attachment 6.40 (.252) bsc
lt3845 24 3845fb linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com ? linear technology corporation 2006 lt 0507 rev b ? printed in usa related parts typical application part number description comments lt1339 high power synchronous dc/dc controller v in up to 60v, drivers 10000pf gate capacitance, i out = <20a ltc ? 1624 switching controller buck, boost, sepic, 3.5v v in 36v; 8-lead so package ltc1702a dual 2-phase synchronous dc/dc controller 550khz operation, no r sense , 3v =

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